Often, in a read only memory (ROM) architecture an N-MOS transistor is used. The gate of the transistor is connected to a word line, the drain of the transistor is connected to a bit line and the source of the transistor is grounded. The bit line is charged to the highest potential even in the idle state. Hence there exists a leakage current due to the voltage drop between the drain and the source of the transistor.
The leakage current is experienced even when the gate of the read only memory transistor is at a logical zero or in other words, in the idle state. In large ROMs the leakage from the ROM array is of a very high magnitude and a dominant component of the total ROM leakage.
The leakage current may be reduced by using a transistor with the source of the transistor virtually grounded. The leakage current may be reduced by using a virtual ground at the source of the transistor. However in such a method, there still exists voltage potential between the source and bulk junction and drain and bulk junction. The source and bulk and drain and bulk junctions contribute junction leakage. In very large ROMs having high number of cells the junction leakage is of large magnitude and a dominant component of the total ROM leakage.
The leakage current may be reduced using a P-MOS architecture. The solution of using P-MOS may result in either a very slow ROM because of the inherent slow nature of P-MOS or a very large ROM if the P-MOS current is increased by increasing its size. The existing ROM architecture standards may not allow the usage of P-MOS architecture.
In light of the forgoing discussion, there is an unmet need for a ROM architecture with minimum leakage drop.